The present invention relates to a semiconductor exposure apparatus for exposing a wafer to the pattern of a mask and, more particularly, to a semiconductor exposure apparatus which is enabled to achieve an exposure, while being freed from complicated processes for changes in the chip size of said wafer or for advancement of the exposure process, always in the exposure position, i.e., without any movement of said wafer after the wafer and the mask have been aligned.
When a semiconductor is to be exposed to a pattern, according to the prior art, the alignment between the mask and the wafer is conducted either by a method such as the off-axis alignment method, using an alignment optical system other than an exposure focusing lens or by a method such as the TTL alignment method, using an exposure focusing lens. The former method is performed by measuring several positions of the peripheral chip on a wafer by means of an alignment optical system and a laser length meter, by computing the chip exposure position on the wafer on the premise that the other chips are accurately arrayed and that the relative positions on the optical axes of the exposure focusing lens and the alignment optical system are accurately known, by moving the chips on the wafer to the computed positions, and by exposing them successively by a stp and repeat method. This method may suffice to measure the several positions of the chips such that the time period required for the chip alignment occupies a short duration in the time period required for exposing all of the wafer but it fails to accurately aligning each chip with the mask. This may raise a serious problem in the future when the exposure pattern becomes finer and finer so that a more accurate alignment is required. The latter method of the prior art for conducting the alignment for each chip by means of the exposure focusing lens is divided into several methods. One example of these methods is shown in FIG. 1. In the example of FIG. 1, a mask 1 has its exposure circuit pattern 4 and alignment marks 112 and 112' are displaced on its face so that an alignment optical system and an exposure optical system do not interfere with each other when the alignment and the exposure are to be executed. For this purpose, as shown in FIG. 2, the alignment between the mask and the chip of the wafer is conducted by aligning the chip alignment marks 122' (and 122) of the wafer and the alignment images 112' (and 112) twice in the order of FIGS. 2(a) and (b), by reading out the wafer position in x and y directions by means of laser length meters LM (and LM'), and by exposing a chip 21 to the image 4' of the circuit pattern of the mask, as shown in FIG. 2(c)-, on the basis of the data read out. In FIG. 1, reference numerals 160, 161 and 161' indicate members for detecting the position of said wafer. As compares with the off-axis alignment method, the TTL alignment method of the prior art herein after called a first alignment moving means has a superior alignment accuracy but has to shift the position of the wafer for execution of the alignment and for the exposure so that the error in the measurement of the laser length meter leads to reduction in the alignment accuracy. There arises another problem in that the time period required for exposing the whole wafer is elongated.
The prior art is exemplified by Japanese Patent Laid-Open Nos. 52-109875, 55-108743, 57-142612 or 58-112330, Japanese Application Nos. 58-243866 and 58-219415 and U.S. Pat. Application Ser. No. 684,292.